1. Field of the Invention
The present invention relates to semiconductor devices, and more specifically to a process for fabricating high density, dynamic random accesss memory, (DRAM), devices.
2. Description of Prior Art
A majority of dynamic random access memory, (DRAM), devices, currently being manufactured in industry, have been fabricated using a stacked capacitor cell, (STC), technology. The basic DRAM memory cell is usually comprised of a transfer gate transistor and a connected capacitor, again usually a version of the stacked capacitor concept. Most designs, employing the STC technology, feature the connected capacitor, directly overlying the transfer gate transsitor, therefore the dimensions of the STC structure is uusally limited by the dimension of the underlying transfer gate structure. The STC structure is most cases is two conductive layers, such as polycrystalline silicon, with a dielectric layer sandwiched between the polycrystalline silicon layers. The ability to store charge is then a function of either the thickness, or the dielectric constant of the dielectric material, or the amount of surface area of the capacitor. Since the thickness of the dielectric can only be reduced to the range of approximately 100 Angstroms, without risking yield or reliability issues, the engineering community has concentrated on increasing the surface area of the STC structure, basically the bottom plate, or the storage node of the STC.
However as previously mentioned, the trend to high density components has resulted in smaller transfer gate structures, thus severely limiting the dimensions of the overlying STC structure. Therefore the industry has attempted to maintain capacitance by increasing the area of the conductive plates, even when the underlying access area, or transfer gate region, is decreasing in dimension. This is accomplished by a process which produces concaves and convexes on the surface of the lower electrode, thus creating increased surface area, without increasing the overall dimension of the DRAM cell. In U.S. Pat. No. 5,290,729, Hayashide, et al, describe a process for producing toughened storage node layers of polycrystalline silicon, or polycrystalline silicon having a surface of concaves and convexes. This is accomplished via specific deposition conditions and subsequent POC13 and oxidation processes. Also Fazan, et al, in U.S. Pat. No. 5,898,091, describe a different form of toughened polysilicon, used for the storage node layer. This invention will present a unique process for creating a polysilicon storage node layer, with a roughened, or rugged surface to increase capacitance. In addition this unique process will offer a large process window, allowing for easy incorporation into manufacturing.